LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY CDRreg IS
    PORT (
        -- '0':start countdown '1':stop countdown
        PCE : IN STD_LOGIC;
        -- '1': stop read and store the countdown number '0':read number
        CDRR : IN STD_LOGIC;
        -- CLOCK signal
        CLK : IN STD_LOGIC;
        -- read data
        CDR : OUT STD_LOGIC
    );
END CDRreg;

ARCHITECTURE archCDRreg OF CDRreg IS
    COMPONENT Count IS
        PORT (
            -- CLOCK signal
            CLK : IN STD_LOGIC;
            -- RESET signal
            RST : IN STD_LOGIC;
            -- CARRY flag
            CARRY : OUT STD_LOGIC
        );
    END COMPONENT;
    SIGNAL temp, NPCE, CARRY : STD_LOGIC;

BEGIN

    NPCE <= NOT PCE;
    U_Count : Count PORT MAP(CLK => CLK, RST => NPCE, CARRY => CARRY);

    registers : PROCESS (CLK)
    BEGIN
        -- implement Master-Slave Register
        IF (CLK'event AND CLK = '1') THEN
            IF (CDRR = '0') THEN
                temp <= CARRY;
            ELSE
                CDR <= temp;
            END IF;
        END IF;
    END PROCESS;

END archCDRreg;